Analog Circuit Design: Scalable Analog Circuit Design by Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund

By Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund

This 10th quantity of "Analog Circuit layout" concentrates on three themes: Scalable Analog Circuits, High-Speed D/A Converters, and RF strength Amplifiers. every one subject is roofed by means of 6 papers, written by way of overseas well-known specialists on that subject. those papers have an instructional nature aimed toward bettering the layout of analog circuits. The publication is split into 3 elements: half I, Scalable Analog Circuit layout describes in 6 papers problems with: scalable high-speed layout, scalable high-resolution mixed-mode ADC and OpAmp layout, scalable high-voltage layout for XDSL, scalability of wire-line entrance ends, reusable IP analog layout, and porting CAD analog layout. half II, High-Speed D/A Converters describes in 6 papers problems with: advent to high-speed D/A converter layout, retargetable 12-bit 200-MHz CMOS present steerage layout, high-speed CMOS D/A converters for upstream cable purposes, static and dynamic functionality barriers, the linearity problem of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis. half III, RF energy Amplifiers describes in 6 papers problems with: method features, review and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF strength amplifier layout in CMOS. "Analog Circuit layout" is a vital reference resource for analog layout engineers and researchers wishing to maintain abreast with the newest advancements within the box. the educational assurance additionally makes it appropriate to be used in an strengthen layout direction.

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778-781, Aug. 1979 2) “A Low Power 12b Analog to Digital Converter with On-Chip Precision Trimming” de Wit et al. IEEE Jnl. of Solid State Circuits, Vol. 28, pp. 455-461, Apr. 1993 (self-calibration) 40 3) “A Self-Calibrating 15 bit CMOS A/D Converter” Lee, Hodges and Gray, IEEE Jnl. of Solid State Circuits, Vol. 19, pp. 813-819, Dec. 1984 4) “Architecture and Algorithm for Fully Digital Correction of Monolithic Pipelined ADCs” Soenen and Geiger, IEEE Trans. Circuits and Systems II, Vol. , IEEE Jnl.

E. between required sourceto-drain punch-through sustainable voltage and component threshold voltage (while large tilt angles are more effective in pushing charge in the DMOS active channel, low tilt angles reduce channel charge and length causing premature punch-through). 45° angle is usually found as the best compromise between these two opposite requirements. 35um) the N-LDMOS P-body layer is to be directly embedded in CMOS epic-pockets. Scaling down the gate oxide thickness requires also a proper LDMOS drain structure engineering.

Analysis will show that this network has a band-stop current transfer function with zero phase shift at a selected high frequency (Fig. 8), chosen to be the amplifier’s unity gain frequency. 39 In this example, optimised for an opamp with unity gain bandwidth of 40MHz and a maximum signal frequency of 1 MHz, it is seen that the effect of the filter is to permit a factor 3 reduction in integrator time constant to give 3x loop gain increase at the maximum signal frequency with zero phase loss at the unity gain bandwidth.

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